Combating Bit Errors From Stuck Cells in Flash Memory Using Novel Information Theory Techniques

Low-density parity-check (LDPC) codes have been successfully deployed in NAND Flash memory based Solid State Drives (SSDs). As Flash memory scales, and has now advanced from planar architectures to three-dimensional ones, defects in the form of stuck cells have increased. Stuck cells are more difficult to correct using LDPC codes because they typically masquerade as reliable bits, but their persistence also offers opportunities to identify and fix them. First, we propose the use of LDPC errors and erasures decoding to erase the bits read from known stuck cells. Second, we use sectionalized Flip-N-Write (FNW) to preprocess the codeword during writes to NAND to minimize bit errors due to stuck cells together with an LDPC inner code. Both proposals have been validated using simulation of a one kilobyte information block encoded in an LDPC code of rate 0.9. LDPC errors and erasures decoding and sectionalized FNW with LDPC result in 1.92× and 1.94× raw bit error rate (RBER) gains, respectively, for soft-decision decoding (SDD).